Higher performance has been demanded of most microprocessors recently. Therefore, higher performance for each microprocessor function is required. Among the most basic functions of microprocessors are various arithmetic operations, such as simple addition. Therefore, an important circuit in a microprocessor is an adder, which adds two or more data values and produces a result.
Besides adding the values of two variables, the adder is also used to calculate memory addresses. Consider for example the accessing of sequential memory addresses by the microprocessor. After accessing the first memory addresses, access of the second memory address requires that the adder add the value of the first memory address to a second value to produce the next memory address. Since the addresses are sequential, in this example the second value to be added to the first address is the number one. The faster the adder can increment a memory address to generate the next address, the faster the microprocessor can access memory, which increases overall performance. An adder, however, conventionally requires larger area for higher performance. A large area of a circuit inevitably leads to a large chip size, which contradicts the current requirements of microprocessors; higher performance coupled with a small area.
Accordingly, what is needed is an incremental arithmetic function for a microprocessor that requires a small area, while providing high-performance. The present invention addresses such a need.